1. Field of the Invention
The present invention relates to a reference buffer and, more specifically, to an on-chip CMOS reference buffer generating reference voltages for use in a pipelined analog to digital converter.
2. Description of the Related Art
Pipelined analog to digital converters (ADC) are widely used in a variety of electronic devices. A pipelined analog to digital converter divides the analog-to-digital conversion task into several consecutive stages. FIG. 1A is a simplified block diagram illustrating a conventional pipelined ADC 100, and FIG. 1B is a simplified block diagram illustrating one of the m-bit analog-to-digital conversion stages of the pipelined ADC 100. The pipelined ADC 100 includes a sample and hold circuit 102, and a plurality (p) of m-bit analog-to-digital conversion (ADC) stages 104, 106, . . . , 108. The sample-and hold circuit 102 holds the analog input voltage (VIN) while the ADC stages 104, 106, . . . , 108 convert the analog input voltage (VIN) to a digital voltage value having n=p×m bits. The ADC stages 104, 106, . . . , 108 have identical structures, one of which is shown in FIG. 1B. In FIG. 1B, the notation “A” refers to analog signals and the notation “D” refers to digital signals.
As shown in FIG. 1B, each of these ADC stages 104, 106, . . . , 108 is comprised of a sample and hold circuit 152, an m-bit ADC (e.g., a flash converter) 154, an m-bit D/A converter (DAC) 156, and an amplifier 160 with a gain of 2m. These ADC stages are usually referred to as Multiplying DACs (MDACs). FIG. 1B is illustrated with reference to the first ADC stage 104, but the other ADC stages have substantially same structures. First, the sample and hold circuit 152 acquires the analog input voltage (VIN). The m-bit ADC (flash converter including comparators) 154 converts the sampled analog input voltage (VIN) signal 153 to m-bit digital data 155, which forms the most significant bits of the digital output. The m-bit digital data 155 is added to the digital data output from the preceding ADC stage (which does not exist in the case of the first stage 104) to generate the accumulated digital output 167 from the first stage to this ADC stage. Referring back to FIG. 1A, note that a time alignment circuit 110 may time-align the digital outputs from the ADC stages 104, 106, . . . , 108 before adding them up. This same m-bit digital data 155 is fed into an m-bit digital-to-analog converter 156, and its output 157 is subtracted from the original sampled signal 159 by the subtractor 158. The residual analog signal 161 is then amplified by the amplifier 160, and the amplified residual analog signal 163 is sent on to the next ADC stage in the pipeline to be sampled and converted in the same manner. This process is repeated through as many stages as are necessary to achieve the desired resolution.
In principle, a pipelined converter with p pipelined stages, each with an m-bit flash converter, can produce a high-speed ADC with a resolution of n=p×m bits using p×(2m−1) comparators in the flash converter ADC 154. For example, a 2-stage pipelined converter with 8-bit resolution requires 30 comparators, and a 4-stage 16-bit ADC requires only 60 comparators. In practice, however, a few additional bits are generated to provide for error correction. Note that as soon as a certain ADC stage finishes processing a sample, it can start processing the next sample while the subsequent ADC stages processes the previous sample, due to the sample-and-hold circuitry 152 embedded within each ADC stage. Such pipelining action accounts for the high throughput.
Referring back to FIGS. 1A and 1B, the pipelined ADCs typically require 3 reference voltages, VREFP, VREFN, and VCOM for use in comparators of the flash converter ADCs 154. In general, VREFP, VREFN, and VCOM in a pipelined ADC satisfy the following relationship:VREFP>VREFNVCOM=(VREFP+VREFN)/2
These reference voltages VREFP, VREFN, and VCOM typically suffer from dynamic kickback from the MDACs and need to settle within the required accuracy for a given number of bits for an ADC within half of the sampling clock period. Typically, the reference voltages are buffered with buffers compensated by external capacitors. FIG. 2 illustrates a conventional reference buffer 200 that modifies and amplifies an initial reference voltage VREFi to generate a reference voltage VREF for use in a pipelined ADC. In the circuitry of FIG. 2, VREFi could be one of VREFPi, VREFNi, and VCOMi, and VREF could be one of VREFP, VREFN, and VCOM. Therefore, it is necessary to have three such conventional reference buffers as illustrated in FIG. 2 to generate all 3 reference voltages VREFP, VREFN, and VCOM for use in a pipelined ADC.
Referring to FIG. 2, the reference buffer 200 is comprised of a buffer 202, a current source, 206, and a transistor 204, which are typically on-chip on the pipelined ADC chip. The buffer 202 receives an initial reference voltage VREFi at the negative input of the buffer 202. The buffer 202 and the transistor 204 form a two-stage amplifier and its driving capability is controlled by its biasing current IB 206.
Note that an external capacitor CEXT 208 is coupled between node 210 and ground (GND) through a pin on the IC (integrated circuit) in a conventional reference buffer 200. The external capacitor 208 is a compensation capacitor for keeping the node 210 at low impedance, providing loop stability, and reducing charge injection to the reference buffer 200. However, adding this external capacitor 208 adds significant cost to the reference buffer 200, and the parasitic inductance caused by the IC pin dedicated to the external capacitor 208 degrades the performance of the pipelined ADC.
Therefore, there is a need for a reference buffer that does not require an external capacitor at its output node.